Methods and Devices for Layered Performance Matching in Hierarchical Memory
Summary
Hierarchical memory is designed to bridge the gap between fast CPU speeds and slower memory speeds. This patent optimizes the data flow across multiple layers of memory (like L1 cache, L2 cache, and main memory) by matching the request rate of an upper layer to the supply rate of the lower layer.
The method adjusts computer architecture parameters, or the schedule of an instruction set, so that the performance of each pair of adjacent layers matches. It addresses the gap between processor and memory speed known as the "memory wall".
Inventors
- Yu-Hang Liu
- Xian-He Sun
Technical Abstract
The present disclosure describes embodiments that relate to methods and devices for layered performance matching in hierarchical memory. The method includes determining a request rate from an ith layer of the hierarchical memory system for each of n layers in the hierarchical memory system. The method also includes determining a supply rate from an (i+1)th layer of the hierarchical memory system for each of the n layers in the hierarchical memory system. The supply rate from the (i+1)th layer of the hierarchical memory system corresponds to the request rate from the ith layer of the hierarchical memory system. The method further includes adjusting a set of computer architecture parameters of the hierarchical memory system or a schedule associated with an instruction set to utilize heterogeneous computing resources within the hierarchical memory system to match a performance of each adjacent layer of the hierarchical memory system.