Timing-Aware Data Prefetching for Microprocessors
Summary
To prevent processors from stalling while waiting for data, "prefetchers" try to guess what data will be needed and load it into fast cache memory ahead of time. However, if data is fetched too early, it might be evicted before it is used, and if fetched too late, the processor still stalls.
This patent introduces "timing-aware" prefetching. By analyzing the exact timing between previous cache misses, the system alters when the next prefetch request is made. The aim is for data to arrive when the processor needs it, neither too early nor too late.
Inventors
- Xian-He Sun
- Yong Chen
- Huaiyu Zhu
Technical Abstract
A method and apparatus for prefetching data from memory for a multicore data processor. A prefetcher issues a plurality of requests to prefetch data from a memory device to a memory cache. Consecutive cache misses are recorded in response to at least two of the plurality of requests. A time between the cache misses is determined and a timing of a further request to prefetch data from the memory device to the memory cache is altered as a function of the determined time between the two cache misses.
Licensing
For licensing inquiries, contact the Gnosis Research Center. The patent covers a timing-aware stride (TAS) prefetcher that uses the timing between cache misses to schedule prefetch requests.
Contact for Licensing