A Generalized Model For Modern Hierarchical Memory System
Authors: H. Najafi, X. Lu, J. Liu, X.-H. Sun
Date: December, 2022
Venue: The 2022 Winter Simulation Conference (WSC), Singapore, December 11-14, 2022
Type: Conference
Abstract
Memory system is critical to architecture design which can significantly impact application performance. Concurrent Average Memory Access Time (C-AMAT) is a model for analyzing and optimizing memory system performance using a recursive definition of the memory access latency along the memory hierarchy. The original C-AMAT model, however, does not provide the necessary granularity and flexibility for handling modern memory architectures with heterogeneous memory technologies and diverse system topology. We propose to augment C-AMAT to take into consideration the idiosyncrasies of individual cache/memory components as well as their topological arrangement in the memory architecture design. Through trace- based simulation, we validate the augmented model and examine the memory system performance with insight unavailable using the original C-AMAT model.